1 commercial temperature range idt23s09t 2.5v zero delay clock buffer, spread spectrum compatible may 2010 2003 integrated device technology, inc. dsc 6396/8 c commercial temperature range the idt logo is a registered trademark of integrated device technology, inc. features: ? phase-lock loop clock distribution ? 10mhz to 133mhz operating frequency ? distributes one clock input to one bank of five and one bank of four outputs ? separate output enable for each output bank ? output skew < 250ps ? low jitter <200 ps cycle-to-cycle ? no external rc network required ? operates at 2.5v v dd ? spread spectrum compatible ? available in soic package functional block diagram idt23s09t 2.5v zero delay clock buffer, spread spectrum compatible description: the idt23s09t is a high-speed phase-lock loop (pll) clock buffer, designed to address high-speed clock distribution applications. the zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133mhz. the idt23s09t is a 16-pin version of the idt23s05t. the idt23s09t accepts one reference input, and drives two banks of four low skew clocks. all parts have on-chip plls which lock to an input clock on the ref pin. the pll feedback is on-chip and is obtained from the clkout pad. in the absence of an input clock, the idt23s09t enters power down, and the outputs are tri-stated. in this mode, the device will draw less than 12a. pll s1 clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 control logic 1 ref s2 16 clkout 8 9 2 3 14 15 6 7 10 11
2 commercial temperature range idt23s09t 2.5v zero delay clock buffer, spread spectrum compatible pin configuration soic top view symbol rating max. unit v dd supply voltage range ?0.5 to +4.6 v v i (2) input voltage range (ref) ?0.5 to +5.5 v v i input voltage range ?0.5 to v (except ref) v dd +0.5 i ik (v i < 0) input clamp current ?50 ma i o (v o = 0 to v dd ) continuous output current 50 ma v dd or gnd continuous current 100 ma t a = 55c maximum power dissipation 0.7 w (in still air) (3) t stg storage temperature range ?65 to +150 c operating commercial temperature 0 to +70 c temperature range notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. the maximum package power dissipation is calculated using a junction temperature of 150c and a board trace length of 750 mils. notes: 1. weak pull down. 2. weak pull down on all outputs. 3. weak pull ups on these inputs. pin description absolute maximum ratings (1) pin name pin number type functional description ref (1) 1 in input reference clock, 3.3v tolerant input clka1 (2) 2 out output clock for bank a clka2 (2) 3 out output clock for bank a v dd 4, 13 pwr 2.5v supply gnd 5, 12 gnd ground clkb1 (2) 6 out output clock for bank b clkb2 (2) 7 out output clock for bank b s2 (3) 8 in select input bit 2 s1 (3) 9 in select input bit 1 clkb3 (2) 10 out output clock for bank b clkb4 (2) 11 out output clock for bank b clka3 (2) 14 out output clock for bank a clka4 (2) 15 out output clock for bank a clkout (2) 16 out output clock, internal feedback on this pin applications: ? sdram telecom datacom pc motherboards/workstations critical path delay designs ref clka1 s2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 clka2 gnd clkb1 clkout clka4 gnd s1 v dd v dd clkb2 clkb3 clkb4 clka3
3 commercial temperature range idt23s09t 2.5v zero delay clock buffer, spread spectrum compatible dc electrical characteristics symbol parameter conditions min. max. unit v il input low voltage level ? 0.7 v v ih input high voltage level 1.7 ? v i il input low current v in = 0v ? 50 a i ih input high current v in = v dd ? 100 a v ol output low voltage standard drive, i ol = 8ma ? 0.3 v v oh output high voltage standard drive, i oh = -8ma 2 ? v i dd_pd power down current ref = 0mhz (s2 = s1 = h) ? 12 a i dd supply current unloaded outputs at 66.66mhz, sel inputs at v dd or gnd ? 32 ma switching characteristics (1,2) symbol parameter conditions min. typ. max. unit t 1 output frequency 15pf load 10 ? 133 mhz duty cycle = t 2 t 1 measured at v dd /2, f out = 66.66mhz 40 50 60 % t 3 rise time measured between 0.7v and 1.7v ? ? 2.5 ns t 4 fall time measured between 0.7v and 1.7v ? ? 2.5 ns t 5 output to output skew all outputs equally loaded ? ? 250 ps t 6a delay, ref rising edge to clkout rising edge (2) measured at v dd /2 ? 0 350 ps t 6b delay, ref rising edge to clkout rising edge (2) measured at v dd /2 in pll bypass mode 1 5 8.7 ns t 7 device-to-device skew measured at v dd /2 on the clkout pins of devices ? 0 700 ps t j cycle-to-cycle jitter measured at 66.66mhz, loaded outputs ? ? 200 ps t lock pll lock time stable power supply, valid clock presented on ref pin ? ? 1 ms notes: 1. ref input has a threshold voltage of v dd /2. 2. all parameters specified with loaded outputs. symbol parameter min. max. unit v dd supply voltage 2.3 2.7 v t a operating temperature (ambient temperature) 0 70 c c l load capacitance 10mhz - 133mhz ? 15 pf c in input capacitance ? 7 pf operating conditions function table (1) s2 s1 clka clkb clkout (2) output source pll shut down l l tri-state tri-state driven pll n l h driven tri-state driven pll n h l driven driven driven ref y h h driven driven driven pll n notes: 1. h = high voltage level. l = low voltage level 2. this output is driven and has an internal feedback for the pll. the load on this ouput can be adjusted to change the skew bet ween the ref and the output.
4 commercial temperature range idt23s09t 2.5v zero delay clock buffer, spread spectrum compatible zero delay and skew control all outputs should be uniformly loaded in order to achieve zero i/o delay. since the clkout pin is the internal feedback for th e pll, its relative loading can affect and adjust the input/output delay. for designs utilizing zero i/o delay, all outputs including clkout must be equally loaded. even if the output is not used, it m ust have a capacitive load equal to that on the other outputs in order to obtain true zero i/o delay. for zero output-to-output skew, all outputs mu st be loaded equally. spread spectrum compatible many systems being designed now use a technology called spread spectrum frequency timing generation. this product is designed not to filter off the spread spectrum feature of the reference input, assuming it exists. when a zero delay buffer is not designed to pass t he spread spectrum feature through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.
5 commercial temperature range idt23s09t 2.5v zero delay clock buffer, spread spectrum compatible v dd outputs clk out c load v dd gnd gnd 0.1 f 0.1 f test circuit for all parameters test circuit output t5 output ref v dd/ 2 t6 output clk out device 1 t7 clk out device 2 v dd/ 2 v dd /2 v dd /2 v dd /2 v dd /2 v dd /2 t2 t1 1.7v 0.7v t3 t4 0.7v 2.5v 0v 1.7v output v dd /2 v dd /2 all outputs rise/fall time input to output propagation delay device to device skew output to output skew duty cycle timing switching waveforms
6 commercial temperature range idt23s09t 2.5v zero delay clock buffer, spread spectrum compatible ordering information idt xxxxx xx x package process device type blank 23s09t-1 dc dcg commercial (0 o c to +70 o c) 2.5v zero delay clock buffer, spread spectrum compatible small outline soic - green corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 clockhelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com part / order number shipping packaging package temperature 23S09T-1DCG tubes 16-pin soic 0 to +70 c 23S09T-1DCG8 tape and reel 16-pin soic 0 to +70 c
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